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[VHDL-FPGA-Verilog] add_16_pipe

Description: 16位加法器的流水线计算,verilog代码，用于FPGA平台。-16 pipelined adder, verilog code for the FPGA platform.
Platform: | Size: 1024 | Author: qjyong | Hits:

[VHDL-FPGA-Verilog] Verilog_Development_Board_Sources

Description: 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Development Board VHDL source code quite welcome, Now she will also be Verilog source contribution to everyone : eight priority encoder, multipliers, Multi-channel selector, binary to BCD, adder, subtraction device, the simple state machine, four comparators, 7 of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng. Traffic lights, digital clock
Platform: | Size: 3151872 | Author: Jawen | Hits:

[VHDL-FPGA-Verilog] 89_full_adder

Description: full adder设计代码，verilog 语言描述，通过modelsim 仿真，quartus综合-full adder design code, verilog language to describe, through the ModelSim simulation, quartus integrated
Platform: | Size: 4096 | Author: shenyunfei | Hits:

[VHDL-FPGA-Verilog] full_adder3

Description: 三位全加器的源代码，和测试代码，用Verilog HDL实现的！-The three full adder of the source code, and test code, using Verilog HDL to achieve!
Platform: | Size: 35840 | Author: 陈吉成 | Hits:

[VHDL-FPGA-Verilog] Mars_EP1C6F_Fundermental_demo(Verilog)

Description: FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。-FPGA development board supporting Verilog HDL code. Chips for the Mars EP1C6F. Are the basic source experiment. Including the adder, subtraction, and multiplier, such as MUX.
Platform: | Size: 1244160 | Author: chenlu | Hits:

[VHDL-FPGA-Verilog] 16bitCLA

Description: 基于Verilog HDL的16位超前进位加法器 分为3个功能子模块-Verilog HDL-based 16-bit CLA is divided into three functional sub-modules
Platform: | Size: 7168 | Author: 韩伟 | Hits:

[VHDL-FPGA-Verilog] adder

Description: FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
Platform: | Size: 1024 | Author: surya | Hits:

[VHDL-FPGA-Verilog] AdderSubtractor

Description: 4-Bit Adder Subtractor Verilog Code. (Complete project)
Platform: | Size: 306176 | Author: gunkaragoz | Hits:

[VHDL-FPGA-Verilog] santhosh_verilog_adder

Description: This has code off multibit Adder. IT is written in verilog. The associated test bench for the verilog code is also attatched within the rar file. Uncompress the rar file and the file name describes the function of each code file.. Comments are welcome. Hope its useful for beginners of verilog.-This has code off multibit Adder. IT is written in verilog. The associated test bench for the verilog code is also attatched within the rar file. Uncompress the rar file and the file name describes the function of each code file.. Comments are welcome. Hope its useful for beginners of verilog.
Platform: | Size: 9216 | Author: santhosh | Hits:

[VHDL-FPGA-Verilog] verilog

Description: verilog语言例题集锦 包含加法器，乘法器，串并转换器等verilog源代码-Example Collection contains verilog language adder, multiplier, and converters, such as string verilog source code
Platform: | Size: 113664 | Author: 刘佳扬 | Hits:

[Energy industry] Verilog

Description: 全加器的Verilog 实现代码 寄存器的Verilog 实现代码-Low-pass filter integral part of full-adder and register the Verilog implementation code
Platform: | Size: 3072 | Author: 田静 | Hits:

[VHDL-FPGA-Verilog] 8BITCONDITIONALSUMADDER

Description: it is verilog code for 8 bit conditional sum adder using veriwe-it is verilog code for 8 bit conditional sum adder using veriwell
Platform: | Size: 29696 | Author: kaleem | Hits:

[VHDL-FPGA-Verilog] FullAdder

Description: This a code programed in Verilog Language. It is Full Adder code designed using Half Adder-This is a code programed in Verilog Language. It is Full Adder code designed using Half Adder..
Platform: | Size: 1024 | Author: Faisal | Hits:

[VHDL-FPGA-Verilog] fpufiles

Description: floating point adder mul and sub in verilog code
Platform: | Size: 19456 | Author: khosro raja | Hits:

[VHDL-FPGA-Verilog] Adder_Kogge_Stone_32bit_With_Test_Bench

Description: verilog source code and test bench of Adder Kogge Stone 32-Bit
Platform: | Size: 528384 | Author: abanuaji | Hits:

[VHDL-FPGA-Verilog] 16bit-CLA

Description: 16 bit carry look ahead adder verilog code
Platform: | Size: 8192 | Author: praveen | Hits:

[VHDL-FPGA-Verilog] L-CLA20_20-code.

Description: DHL CLA20_20 development with the Verilog bit ahead carry adder code.
Platform: | Size: 373760 | Author: 吴成芯 | Hits:

[source in ebook] BCDadder

Description: cource code for BCD adder in verilog language
Platform: | Size: 8192 | Author: zebl | Hits:

[Other] add8

Description: 8*8位全加器的代码 verilog语言，包含测试文件(8*8-bit full adder code verilog)
Platform: | Size: 33792 | Author: 北冥燚 | Hits:

[VHDL-FPGA-Verilog] code

Description: adder 18b trong chuong trinh verilog
Platform: | Size: 3072 | Author: tailuong | Hits:
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